
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity div_remainder_handler is
	port(
	remainder : in STD_LOGIC_VECTOR(31 downto 0);
	numerator_sign : in STD_LOGIC;
	is_signed : in STD_LOGIC;
	
	final_remainder : out STD_LOGIC_VECTOR(31 downto 0)
	
	);
end div_remainder_handler;

architecture Behavioral of div_remainder_handler is
	
begin
	process(remainder, numerator_sign, is_signed)
	begin
		if (is_signed ='1' and numerator_sign='1') then
			final_remainder <= STD_LOGIC_VECTOR(-signed(remainder));
		else
			final_remainder <= remainder;
		end if;
	end process;

end Behavioral;

